1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including a dielectric having a low permittivity to enhance device performance.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep submicron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip. In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the involved transistor elements. As the channel length of these elements has now reached 0.18 μm and less, it turns out, however, that the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased circuit density, by the close proximity of the interconnect lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to a reduced cross-sectional area. The parasitic RC time constants therefore require the introduction of a new type of dielectric material, preferably in combination with a highly conductive metal.
Traditionally, metallization layers are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride, with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities, in highly sophisticated integrated circuits, aluminum is commonly replaced by copper having a significantly lower electrical resistance and a higher resistivity against electromigration. Moreover, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>5) are increasingly replaced by low-k materials to reduce parasitic capacitances. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper metallization layer is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in higher amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes so that, consequently, the so-called damascene technique is employed in forming metallization layers including copper lines. Typically, in the damascene technique, the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper by plating methods, such as electroplating or electroless plating. For forming vias providing electrical connection from an overlying copper line to an underlying copper line of a lower metallization layer, the vias and the trenches may be filled in a single process so that the vias and trenches have to be patterned prior to filling in the copper. A corresponding technique, also referred to as a dual damascene technique, is carried out for a conventional dielectric layer stack by providing a silicon dioxide layer and an intermediate silicon nitride layer that acts as an etch stop layer for the trench etch and a second silicon dioxide layer formed thereon. Subsequently, a via may be etched in the upper silicon dioxide layer and the silicon nitride layer may be opened for a subsequent via etch, wherein prior to etching the via into the lower silicon dioxide layer a respective photoresist mask for the trench etching of the upper silicon dioxide layer is formed. Then, the trench etch and the lower via etch may be performed simultaneously, wherein the depth of the trench is reliably controlled by the silicon nitride etch stop layer. When replacing the high-k material silicon dioxide by a low-k material, the situation in forming the via and trench is quite different, as the provision of an intermediate etch stop layer, such as the silicon nitride layer exhibiting a high k value, may unduly increase the permittivity of the entire dielectric stack. To obtain a minimum permittivity, the intermediate etch stop layer is commonly omitted. A frequently used etch scheme for forming trenches and vias may be performed according to the sequence as will now be described with reference to FIGS. 1a-1d. 
FIG. 1a schematically shows a cross-sectional view of a semiconductor structure 100 including a substrate 101 that may include circuit elements, such as transistors, capacitors, resistors and the like and may include one or more metallization layers similar to a metallization layer to be formed on the substrate 101. A bottom etch stop layer 102 that also serves as a diffusion barrier is formed on the substrate 101 with a thickness sufficient to reliably stop or slow down an etch process to avoid damage of the underlying substrate 101 and to substantially prevent diffusion of a metal, such as copper, into underlying materials. In highly sophisticated applications, it is preferred that the etch stop layer 102 is provided as a low-k material that replaces, for example, a silicon nitride layer. For instance, a silicon carbide nitride (SiCN) layer may be used as the etch stop layer 102, which is also referred to as “barrier low-k” (BLOK). A low-k dielectric layer 103 is formed on the etch stop layer 102. One viable candidate for a low-k material for the dielectric layer 103 is hydrogen-containing silicon-oxy-carbide (SiCOH) having a permittivity of approximately 2. In some applications, an anti-reflective coating 104 formed on the dielectric layer 103 may be necessary for patterning the dielectric layer 103. Finally, a patterned photoresist mask 105 is formed over the dielectric layer 103, with an opening 106 formed therein, that represents the dimensions of the via to be formed in the dielectric layer 103. The process techniques required for forming the semiconductor structure 100 shown in FIG. 1a are well established and well known and thus a description thereof will be omitted.
Subsequently, an anisotropic etch process is carried out, wherein the photoresist mask 105 acts as an etch mask. FIG. 1b schematically shows the semiconductor structure 100 after completion of the anisotropic etch process. A via 107 is formed in the dielectric layer 103 in accordance with the dimensions of the opening 106 (FIG. 1a).
FIG. 1c schematically depicts the semiconductor structure 100 with a photoresist mask 109 having an opening 108 in conformity with the design dimensions of a trench to be formed. Optionally, the resist mask 109 may be designed such that the bottom of the opening 107 is also covered. Subsequently, the substrate 101 is anisotropically etched, wherein process parameters, especially the process time, have to be precisely controlled to obtain a required depth for the trench to be formed.
FIG. 1d schematically shows the semiconductor structure 100 after completion of the anisotropic etch process with a trench 110 formed in an upper portion of the dielectric layer 103. A depth 111 of the trench 110 is thus determined by the etch process parameters. It thus appears that although a simple and effective process sequence may be established by providing the dielectric layer 103 without an intermediate etch stop, thereby resulting in an optimum low-k value, any variations of the anisotropic etch process may result in a depth variation and may, therefore, entail a variation of the electric performance of a copper line formed in the trench 110, as the resistance thereof depends on the cross-section of the trench 110.
Since a copper line resistance variation may have an adverse impact on the device performance, it would therefore be highly desirable to provide for a dual damascene scheme that allows an optimum low-k value for a given dielectric material without being prone to significant trench depth variations.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.